On the edge, measured.

The independent register for NPUs that leave the datacenter behind — Hailo-8, 8L, 10H, 15H first, with Jetson Orin, Coral, Rockchip, Qualcomm and the Apple Neural Engine held next to them. Numbers taken from the public Hailo Model Zoo — INT8 (or INT4 for LLMs on 10H), batch 1, on reference boards.

5 Hailo chips covered · 21 benchmarked models · 9 detection / seg variants · 3 on-device LLMs on Hailo-10H.

Seven watts, to forty TOPS.

Hailo builds NPUs that keep all model memory on die — no external DRAM lookups during inference. That decision buys predictable latency and very high perf-per-watt; it also means the model has to fit, or be partitioned by the Hailo compiler.

Family

Accelerator · Vision Processor

Quantisation

INT8 default · INT4 for LLMs on 10H

Runtime

HailoRT · x86 · ARM · Raspberry Pi

Compile

Dataflow Compiler → .hef

The wider edge shelf.

Hailo is the primary lens of this register, but the edge shelf is wider. Jetson Orin owns the CUDA-native robotics lane; Google Coral is the old reliable for TFLite classifiers; Rockchip and Qualcomm ship inside SBCs and phones; the Apple Neural Engine quietly runs CoreML on every M-series machine.

Numbers from vendor product pages. Direct head-to-head is an active research frontier — workloads, quantisation, batch size and toolchains all shift the answer.

Eight workloads. One chip at a time.

The same chip is fast at vision and slow at OCR; Hailo-10H runs an 8B LLM at decode-interactive speed and, in the same envelope, clears 275 FPS on YOLOv8n. Each panel ends at a real number from the Hailo Model Zoo.

Pre-compiled, per chip.

FPS from the public Hailo Model Zoo. INT8, batch 1, reference boards. LLM rows are INT4 decode tok/s with 2K context on Hailo-10H. A dash means the model is not officially compiled for that chip.

Deeper reads, per chip family.

Each sub-page carries its own evidence table. This hub is the index; the work is below.

Neighbouring registers.